sfence.w.inval
Order writes before sfence
The sfence.w.inval instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent sinval.vma instructions executed by the same hart.
Execution
if (mode() == PrivilegeMode::U) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if (CSR[misa].H == 1 && mode() == PrivilegeMode::VU) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}
VmaOrderType vma_type;
vma_type.global = true;
vma_type.smode = true;
if (CSR[misa].H == 1) {
vma_type.vsmode = true;
vma_type.gstage = true;
}
order_pgtbl_writes_before_vmafence(vma_type);Exceptions
This instruction may result in the following synchronous exceptions:
-
IllegalInstruction
-
VirtualInstruction