prefetch.i

Cache block prefetch for instruction fetch

A prefetch.i instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by an instruction fetch in the near future.

Assembly format

prefetch.i imm(xs1)

Decode Variables

signed Bits<12> imm = sext({$encoding[31:25], 5'd0}, 12);
Bits<5> xs1 = $encoding[19:15];

Execution

XReg address = X[xs1] + $signed(imm << 5);
prefetch_instruction(address);

Encoding

svg

Defining extension

Access

M

Always

Containing profiles

  • Mandatory: RVA22S64, RVA22U64, RVA23S64, RVA23U64, RVB23S64, RVB23U64

  • Optional: None