vsip

Virtual Supervisor Interrupt Pending

The vsip register is a VSXLEN-bit read/write register that is VS-mode’s version of the sip CSR. When V=1, instructions that normally access sip instead access vsip. It holds the pending interrupt status for supervisor-level traps in a virtualized environment.

However, interrupts directed to HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1.

The standard portion (bits 15:0) includes individual interrupt-pending bits.

Attributes

Requirement

Defining extensions

H	Hypervisor

CSR Address

0x244

Virtual CSR Address

0x144

Length

* 32 when CSR[hstatus].VSXL == 0 * 64 when CSR[hstatus].VSXL == 1

Privilege Mode

Format

This CSR format changes dynamically.

Figure 1. vsip Format when CSR[hstatus].VSXL == 0

Figure 2. vsip Format when CSR[hstatus].VSXL == 1

Field Summary

Name	Location	Type	Reset Value
vsip.SSIP	1	RW-H	UNDEFINED_LEGAL
vsip.STIP	5	RW-H	UNDEFINED_LEGAL
vsip.SEIP	9	RW-H	UNDEFINED_LEGAL
vsip.LCOFIP	13	RW-H	UNDEFINED_LEGAL

Name

Location

Type

Reset Value

vsip.SSIP

RW-H

UNDEFINED_LEGAL

vsip.STIP

RW-H

UNDEFINED_LEGAL

vsip.SEIP

RW-H

UNDEFINED_LEGAL

vsip.LCOFIP

RW-H

UNDEFINED_LEGAL

Fields

`SSIP`

Location: 1
Description: Supervisor Software Interrupt Pending Indicates a pending software interrupt at the supervisor level. Read-only zero when hideleg.VSSI == 0, else aliased to hip.VSSIP.
Type: RW-H
Reset value: UNDEFINED_LEGAL

`STIP`

Location: 5
Description: Supervisor Timer Interrupt Pending Indicates a pending timer interrupt at the supervisor level. Read-only zero when hideleg.VSTI == 0, else aliased to hip.VSTIP.
Type: RW-H
Reset value: UNDEFINED_LEGAL

`SEIP`

Location: 9
Description: Supervisor External Interrupt Pending Indicates a pending external interrupt at the supervisor level. Read-only zero when hideleg.VSEI == 0, else aliased to hip.VSEIP.
Type: RW-H
Reset value: UNDEFINED_LEGAL

`LCOFIP`

Location: 13
Description: Local Counter Overflow Interrupt Pending Indicates an overflow of a local counter. Read-only zero when hideleg.LCOFI == 0, else aliased to sip.LCOFIP.
Type: RW-H
Reset value: UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SSIP = if (CSR[hideleg].VSSI == 1) {
  CSR[hip].VSSIP = csr_value.SSIP;
}

STIP = if (CSR[hideleg].VSTI == 1) {
  CSR[hip].VSTIP = csr_value.STIP;
}

SEIP = if (CSR[hideleg].VSEI == 1) {
  CSR[hip].VSEIP = csr_value.SEIP;
}

LCOFIP = if (CSR[hideleg].LCOFI == 1) {
  CSR[sip].LCOFIP = csr_value.LCOFIP;
}

Software read

This CSR may return a value that is different from what is stored in hardware.

XReg result = 0;
if (CSR[hideleg].VSSI == 1) {
  result[1] = CSR[hip].VSSIP;
}
if (CSR[hideleg].VSTI == 1) {
  result[5] = CSR[hip].VSTIP;
}
if (CSR[hideleg].VSEI == 1) {
  result[9] = CSR[hip].VSEIP;
}
if (implemented?(ExtensionName::Sscofpmf)) {
  if (CSR[hideleg].LCOFI == 1) {
    result[13] = CSR[sip].LCOFIP;
  }
}
return result;