hvip

Hypervisor Virtual Interrupt Pending Register

The hvip register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts.

Attributes

Requirement

H

Defining extensions

H

Hypervisor

CSR Address

0x645

Length

* 32 when CSR[mstatus].SXL == 0 * 64 when CSR[mstatus].SXL == 1

Privilege Mode

S

Format

This CSR format changes dynamically.

hvip Format when CSR[mstatus].SXL == 0
Figure 1. hvip Format when CSR[mstatus].SXL == 0
hvip Format when CSR[mstatus].SXL == 1
Figure 2. hvip Format when CSR[mstatus].SXL == 1

Field Summary

Name Location Type Reset Value

hvip.VSEIP

10

RW

UNDEFINED_LEGAL

hvip.VSTIP

6

RW

UNDEFINED_LEGAL

hvip.VSSIP

2

RW

UNDEFINED_LEGAL

Fields

VSEIP

Location

10

Description

Pending interrupt bit for VS-level external interrupts. This bit is writable and is set to 1 to assert a VS-level external interrupt. TODO: assert the interrupt

Type

RW

Reset value

UNDEFINED_LEGAL

VSTIP

Location

6

Description

Pending interrupt bit for VS-level timer interrupts. This bit is writable and is set to 1 to assert a VS-level timer interrupt. TODO: assert the interrupt

Type

RW

Reset value

UNDEFINED_LEGAL

VSSIP

Location

2

Description

Pending interrupt bit for VS-level software interrupts. This bit is writable and is set to 1 to assert a VS-level software interrupt. TODO: assert the interrupt

Type

RW

Reset value

UNDEFINED_LEGAL