fcvt.wu.s

Floating-Point Convert Single-Precision to Unsigned Word

Converts a floating-point number in floating-point register fs1 to an unsigned 32-bit integer in integer register xd. For XLEN >32, fcvt.wu.s sign-extends the 32-bit result to the destination register width.

If the rounded result is not representable as a 32-bit unsigned integer, it is clipped to the nearest value and the invalid flag is set.

The range of valid inputs and behavior for invalid inputs are:

Value

Minimum valid input (after rounding)

0

Maximum valid input (after rounding)

2^32 - 1

Output for out-of-range negative input

0

Output for −∞

0

Output for out-of-range positive input

2^32 - 1

Output for +∞ for NaN

2^32 - 1

All floating-point to integer and integer to floating-point conversion instructions round according to the rm field.

A floating-point register can be initialized to floating-point positive zero using fcvt.s.w xd, x0, which will never set any exception flags.

All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.

Assembly format

fcvt.wu.s xd, fs1, rm

Decode Variables

Bits<5> fs1 = $encoding[19:15];
Bits<3> rm = $encoding[14:12];
Bits<5> xd = $encoding[11:7];

Execution

check_f_ok($encoding);
RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
X[xd] = $signed(f32_to_ui32(F[fs1], rounding_mode));

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction

Encoding

svg

Defining extension

F

Access

M

Always

Containing profiles

  • Mandatory: RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23S64, RVA23U64, RVB23S64, RVB23U64

  • Optional: RVI20U32, RVI20U64