hip

Hypervisor Interrupt Pending Register

The hip register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level. It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts.

Attributes

Requirement

Defining extensions

H	Hypervisor

CSR Address

0x608

Length

* 32 when CSR[mstatus].SXL == 0 * 64 when CSR[mstatus].SXL == 1

Privilege Mode

Format

This CSR format changes dynamically.

Figure 1. hip Format when CSR[mstatus].SXL == 0

Figure 2. hip Format when CSR[mstatus].SXL == 1

Field Summary

Name	Location	Type
hip.SGEIP	12	RO-H
hip.VSEIP	10	RO-H
hip.VSTIP	6	RO-H
hip.VSSIP	2	RO-H

Fields

`SGEIP`

Location: 12
Description: Pending interrupt bit for supervisor guest external interrupts (SGEI). This bit is 1 if and only if the logical AND of hgeip and hgeie is nonzero.
Type: RO-H
Reset value: 0

`VSEIP`

Location: 10
Description: Pending interrupt bit for VS-level external interrupts (VSEI). This bit is the logical OR of vseip from hvip, the interrupt from hgeip selected by hstatus.VGEIN, and any other external interrupt signal directed to VS-level.
Type: RO-H
Reset value: 0

`VSTIP`

Location: 6
Description: Pending interrupt bit for VS-level timer interrupts (VSTI). This bit is the logical OR of vstip from hvip and any other timer interrupt directed to VS-level.
Type: RO-H
Reset value: 0

`VSSIP`

Location: 2
Description: Pending interrupt bit for VS-level software interrupts (VSSI). This bit is an alias of the vssip bit in hvip.
Type: RO-H
Reset value: 0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SGEIP = csr_value.SGEIP
VSEIP = csr_value.VSEIP
VSTIP = csr_value.VSTIP
VSSIP = # VSSIP in hip is an alias of VSSIP in hvip
CSR[hvip].VSSIP = csr_value.VSSIP;
return csr_value.VSSIP;

Software read

This CSR may return a value that is different from what is stored in hardware.

XReg res = 0;
if (($bits(CSR[CSR[hgeie]]) & $bits(CSR[CSR[hgeip]])) != 0) {
  res[12] = 1'b1;
}
if (CSR[hvip].VSEIP == 1'b1) {
  res[10] = 1'b1;
}
if (implemented?(ExtensionName::Sstc)) {
  if ((CSR[hvip].VSTIP == 1'b1) || read_mtime() + CSR[htimedelta].DELTA) >= CSR[vstimecmp].TIME {
    res[6] = 1'b1;
  }
} else {
  if (CSR[hvip].VSTIP == 1'b1) {
    res[6] = 1'b1;
  }
}
if (CSR[hvip].VSSIP == 1'b1) {
  res[2] = 1'b1;
}
return res;