vle8.v

Vector 8-bit unit-stride load

Loads 8-bit elements from memory starting at address in xs1 register, using vector mask vm, and stores results in vector register vd. The effective element width is 8 bits regardless of SEW setting. Supports vector masking and follows vector tail policy.

Assembly format

vle8.v vd, (xs1), vm

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> xs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

XReg virtual_address = X[xs1];
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
  U32 start_bit_pos = i * 8;
  U32 end_bit_pos = start_bit_pos + 7;
  V[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
}
CSR[vstart].VALUE = 0;

Exceptions

This instruction may result in the following synchronous exceptions:

  • LoadAccessFault

  • LoadAddressMisaligned

  • LoadPageFault

Encoding

svg

Defining extension

Zvl32b

Access

M

Always

Containing profiles

  • Mandatory: None

  • Optional: None