vnsra.wv
Vector narrowing signed shift right arithmetic
Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];