vwmaccus.vx
Vector widening unsigned multiply-add with scalar, signed
Performs widening unsigned multiplication on elements from vector register vs2 and scalar register xs1, adds the signed result to elements from vector register vd, and stores the final results in vector register vd, using vector mask vm.
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];