vfwadd.vf
Vector floating-point widening addition with scalar
Performs floating-point addition on elements from vector register vs2 and floating-point scalar register fs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> fs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];