sinval.vma
Invalidate cached address translations
The sinval.vma instruction invalidates any address-translation cache entries that an sfence.vma instruction with the same values of xs1 and xs2 would invalidate. However, unlike sfence.vma, sinval.vma instructions are only ordered with respect to sfence.vma, sfence.w.inval, and sfence.inval.ir instructions as defined below.
Execution
XReg vaddr = X[xs1];
Bits<ASID_WIDTH> asid = X[xs2][ASID_WIDTH - 1:0];
if (CSR[mstatus].TVM == 1 && mode() == PrivilegeMode::S) || (mode() == PrivilegeMode::VS) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if (CSR[misa].H == 1 && CSR[hstatus].VTVM == 1 && mode() == PrivilegeMode::VS) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}
if (mode() == PrivilegeMode::U) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if (CSR[misa].H == 1 && mode() == PrivilegeMode::VU) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}
VmaOrderType vma_type;
if (CSR[misa].H == 1 && mode() == PrivilegeMode::VS) {
vma_type.vsmode = true;
vma_type.single_vmid = true;
vma_type.vmid = CSR[hgatp].VMID;
} else {
vma_type.smode = true;
}
if ((xs1 == 0) && (xs2 == 0)) {
vma_type.global = true;
invalidate_translations(vma_type);
} else if ((xs1 == 0) && (xs2 != 0)) {
vma_type.single_asid = true;
vma_type.asid = asid;
invalidate_translations(vma_type);
} else if ((xs1 != 0) && (xs2 == 0)) {
if (canonical_vaddr?(vaddr)) {
vma_type.single_vaddr = true;
vma_type.vaddr = vaddr;
invalidate_translations(vma_type);
}
} else {
if (canonical_vaddr?(vaddr)) {
vma_type.single_asid = true;
vma_type.asid = asid;
vma_type.single_vaddr = true;
vma_type.vaddr = vaddr;
invalidate_translations(vma_type);
}
}Exceptions
This instruction may result in the following synchronous exceptions:
-
IllegalInstruction
-
VirtualInstruction