vabs.v
Vector Single-Width Signed Integer Absolute
This instruction is defined by:
Synopsis
An absolute value operation is performed on each element of vs2, storing the result in vector register vd according to mask vm.
vabs.v supports SEW of 8, 16, and 32 when Zve32x is implemented. When Zve64x is implemented, vabs.v also supports SEW of 64.
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];
Execution
-
Pruned, XLEN == 64
-
Original
VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = 17'128;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
vlmax = (64'128 << state.log2_lmul) >> state.log2_sew;
} else {
vlmax = (64'128 >> state.log2_lmul) >> state.log2_sew;
}
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i) {
U32 start_bit_pos = i * state.sew;
U32 end_bit_pos = start_bit_pos pass:[+] state.sew - 1;
if pass:[(]vm == 1'b1 || V[0][i:i] == 1'b1) {
if pass:[(]V[vs2][end_bit_pos:end_bit_pos] == 1'b1) {
V[vd][end_bit_pos:start_bit_pos] = -$signed(++V[vs2][end_bit_pos:start_bit_pos]);
} else {
V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos];
}
}
}
CSR[vstart].VALUE = 0;
VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = VLEN;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
} else {
vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
}
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i) {
U32 start_bit_pos = i * state.sew;
U32 end_bit_pos = start_bit_pos pass:[+] state.sew - 1;
if pass:[(]vm == 1'b1 || V[0][i:i] == 1'b1) {
if pass:[(]V[vs2][end_bit_pos:end_bit_pos] == 1'b1) {
V[vd][end_bit_pos:start_bit_pos] = -$signed(++V[vs2][end_bit_pos:start_bit_pos]);
} else {
V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos];
}
}
}
CSR[vstart].VALUE = 0;